The present invention relates to amplification type solid-state image pickup devices and, more particularly, to an amplification type solid-state image pickup device which includes a plurality of pixels each having a photoelectric conversion element and a transfer transistor for transferring signal charge of the photoelectric conversion element, in which signals from the pixels are amplified and outputted, respectively, to a signal line common to the pixels.
Generally, there has been widely used an amplification type solid-state image pickup device which has a pixel section having an amplification function and a scanning circuit placed around the pixel section and in which pixel data are read from the pixel section by the scanning circuit. Particularly well known are APS (Active Pixel Sensor) type image sensors which are formed of CMOS (Complementary Metal-Oxide Semiconductor) being advantageous to integration of the pixel section with its surrounding drive circuit and signal processing circuit.
In the APS type image sensor, normally, a photoelectric conversion section, an amplification section, a pixel select section and a reset section are included in one pixel. Therefore, constituting an APS type image sensor typically involves the use of three to four MOS transistors (Tr) in addition to the photoelectric conversion section formed of photodiodes. However, providing three to four MOS transistors per pixel would be a limitation to a reduction of the pixel size. This accounts for usefulness of the technique that a plurality of photoelectric conversion sections share one amplification section to decrease the number of transistors per pixel. In this case, however, the more the number of sharing photoelectric conversion sections increases, the more the charge-voltage conversion efficiency η (=Vsig/Qsig), the ratio of converted voltage signal Vsig to signal charge Qsig from photodiodes, decreases.
Accordingly, as a solution to this issue, the present inventor invented an amplification type solid-state image pickup device that involves no decrease of the charge-voltage conversion efficiency η, as shown in FIG. 10 (see JP 2005-217607 A).
This two-dimensional amplification type solid-state image pickup device, as shown in FIG. 10, is composed of: photoelectric conversion sections each having a photodiode 101 as a photoelectric conversion element and a transfer transistor 102 for transferring signal charge of the photodiode 101; an amplification section having a charge detection node 108 to which output terminals of the transfer transistors 102 are connected in common, an amplification transistor 103A to which a signal of the charge detection node 108 is inputted, a reset transistor 106 connected between the charge detection node 108 and an output terminal of the amplification transistor 103A, a capacitor 107 (its capacity denoted by Cin) connected between the charge detection node 108 and the output terminal of the amplification transistor 103A, a select transistor 104 connected between the output terminal of the amplification transistor 103A and a vertical signal line 109, and a capacitor 111 (its capacity denoted by Cup) connected between the charge detection node 108 and a boost signal line; and a constant-current load transistor 103B connected between the vertical line 109 and a power source.
As shown in FIG. 11, in a period T1, a gate drive signal φS(n) applied to the select transistor 104 goes high level, and a gate drive signal φR(n) applied to the reset transistor 106 goes high level, causing voltages of the charge detection node 108 and the vertical signal line 109 to be reset to a constant voltage Vo (reset level) by action of a constant-current load source-grounded inverting amplifier composed of the amplification transistor 103A and the constant-current load transistor 103B.
The reset level Vo is determined as follows. That is, the circuit of the constant-current load source-grounded inverting amplifier composed of the amplification transistor 103A and the constant-current load transistor 103B as described above is represented as shown in FIG. 12. In this case, given an input Vin and an output Vout of this inverting amplifier, when the transistors 104, 106 turn on so as to be short-circuited, it follows that Vout=Vin, and therefore the reset level Vo is determined as an intersection point with a straight line that Vout=Vin, as shown in FIG. 13.
Next, in a period T2 shown in FIG. 11, the gate drive signal φR(n) goes low level, causing the reset transistor 106 to turn off, while the gate drive signal φS(n) remains high level, with the select transistor 104 is in the on state. Therefore, an output (reset level Vo) resulting from inversion and amplification of the voltage of the charge detection node 108 is read via the on-state select transistor 104 to the vertical signal line 109.
In a succeeding period T3, the gate drive signal φS(n) goes low level, causing the select transistor 104 to turn off. In this case, a gate drive signal φT(n,1) goes high level, causing the transfer transistor 102 to turn on, so that signal charge stored in the photodiode 101 is transferred through the on-state transfer transistor 102 to the charge detection node 108. Further, in synchronization with the gate drive signal φT(n,1), a boost signal φC(n) goes high level, where the potential of the charge detection node 108 is deepened by capacitive coupling via the capacitor 111 (with capacitance Cup). Thus, the charge transfer from the photodiode 101 to the charge detection node 108 is accelerated.
In a next period T4, the gate drive signal φT(n,1) goes low level, causing the transfer transistor 102 to turn off. Also, the boost signal φC(n) goes low level, so that the potential change of the charge detection node 108 by the capacitive coupling via the capacitor 111 is canceled. As a result, a voltage (signal level) shifted by the signal charge transfer in the period T3 from the reset level (voltage Vo) in the period T2 is held at the charge detection node 108. This signal level is amplified by the constant-current load source-grounded inverting amplifier composed of the amplification transistor 103A and the constant-current load transistor 103B, and read through the on-state select transistor 104 to the vertical signal line 109.
Thereafter, a difference signal between the reset level of the period T2 read to the vertical signal line 109 and the signal level of the period T4 can be extracted as an effective signal due to charge generated by light that has been incident on the pixel.
After one horizontal scanning period (1H period), operations similar to those of the foregoing periods T1 to T4 are performed by driving the gate drive signal φT(n,2).
In this way, iterating the operations of the periods T1 to T4 to an iteration number of k times for each one horizontal scanning period (1H period) allows signals derived from the k photodiodes 101 for each column to be respectively amplified and outputted to the vertical signal line 109.
Now, given a charge amount Qsig transferred from the photodiodes 101 and a gain A of the constant-current load source-grounded inverting amplifier, an effective signal to be read isVsig=A·Qsig/[CFD+Cup+(1+A)Cin]  (1)where the gain A of the constant-current load source-grounded inverting amplifier is
                    A        =                  gm          ·                                    ron              ·              rop                                      ron              +              rop                                                          (        2        )            In Equation (2), gm represents a transconductance of the amplification transistor 103A, ron represents an output resistance of the amplification transistor 103A, and rop represents an output resistance of the constant-current load transistor 103B.
In particular, when the gain A is very large, it is derived from Equation (1) thatVsig≈Qsig/Cin   (3)Therefore, the charge-voltage conversion efficiency η results inη=Vsig/Qsig=1/Cin  (4)As can be seen from Equation (4), when the gain A is very large, there are substantially almost no effects of the capacity CFD of the charge detection node 108 on the outputted signal. Accordingly, even if the number of pixels connected to one another in the column direction so that the capacity CFD becomes large, there occurs no decrease of the charge-voltage conversion efficiency η.
However, the technique of JP 2005-217607 A is subject to occurrence of the following problem. That is, the constant-current load source-grounded inverting amplifier has to drive the vertical signal line 109 of a large load capacity in a short period. On the other hand, a relationship among an output resistance Zout of the constant-current load source-grounded inverting amplifier, the gain A and a bias current Ibias is represented by the following equation:Zout∝(Ibias)−1  (5)gm∝(Ibias)1/2  (6)∴ A∝(Ibias)−1/2  (7)
Therefore, driving the vertical signal line 109 of a large load capacity involves increasing the bias current Ibias to lower the output resistance Zout. However, doing so would lower the gain A in turn, leading to a problem that the charge-voltage conversion efficiency η would decrease.
For example, when a load 1 pF of the vertical signal line 109 needs to be driven at 1 μS, it follows that Zout=140 kΩ, where the resulting gm=0.25 mS or so, yielding a result that gain A=35.
Now, with an arrangement that eight pixels share one switched capacitor amplifier unit 106, 107, 103A, 111, ifCFD=2 fF×8=16 fFCup=CFDCin=1 fF,then[CFD+Cup+(1+A)Cin]/A=1.94 fF,which is a value about twice larger than Cin, so that the charge-voltage conversion efficiency η declines.